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Single, Low Voltage Digitally Controlled Potentiometer (XDCPTM)
ISL23315
The ISL23315 is a volatile, low voltage, low noise, low power, I2C BusTM, 256 Taps, single digitally controlled potentiometer (DCP), which integrates DCP core, wiper switches and control logic on a monolithic CMOS integrated circuit. The digitally controlled potentiometer is implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the I2C bus interface. The potentiometer has an associated volatile Wiper Register (WR) that can be directly written to and read by the user. The contents of the WR controls the position of the wiper. When powered on, the ISL23315's wiper will always commence at mid-scale (128 tap position). The low voltage, low power consumption, and small package of the ISL23315 make it an ideal choice for use in battery operated equipment. In addition, the ISL23315 has a VLOGIC pin allowing down to 1.2V bus operation, independent from the VCC value. This allows for low logic levels to be connected directly to the ISL23315 without passing through a voltage level shifter. The DCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.
Features
* 256 resistor taps * I2C serial interface - No additional level translator for low bus supply - Two address pins allow up to four devices per bus * Wiper resistance: 70 typical @ VCC = 3.3V * Shutdown Mode - forces the DCP into an end-to-end open circuit and RW is shorted to RL internally * Power-on preset to mid-scale (128 tap position) * Standby current <2.5A max * Shutdown current <2A max * Power supply - VCC = 1.7V to 5.5V analog power supply - VLOGIC = 1.2V to 5.5V I2C bus/logic power supply * DCP terminal voltage from 0V to VCC * 10k, 50k or 100k total resistance * Extended industrial temperature range: -40C to +125C * 10 Ld MSOP or 10 Ld TQFN packages * Pb-free (RoHS compliant)
Applications
* Power supply margining * RF power amplifier bias compensation * LCD bias compensation * Laser diode bias compensation
10000
VREF
8000 RESISTANCE ()
6000
ISL23315
+ ISL28114
VREF_M
4000
2000
0
0
50
100
150
200
250
TAP POSITION (DECIMAL)
FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP POSITION, 10k DCP
FIGURE 2. VREF ADJUSTMENT
December 15, 2010 FN7778.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2010. All Rights Reserved Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners
ISL23315 Block Diagram
VLOGIC VCC
SCL SDA A1 A0 I/O BLOCK LEVEL SHIFTER
POWER-UP INTERFACE, CONTROL AND STATUS LOGIC
RH WR VOLATILE REGISTER AND WIPER CONTROL CIRCUITRY
RL RW GND
Pin Configurations
ISL23315 (10 LD MSOP) TOP VIEW
VLOGIC SCL SDA A0 A1 1 2 3 4 5 10 9 8 7 6 GND VCC RH RW RL
Pin Descriptions
MSOP 1 2 3 4 TQFN 10 1 2 3 SYMBOL VLOGIC SCL SDA A0 DESCRIPTION I2C bus /logic supply. Range 1.2V to 5.5V Logic Pin - Serial bus clock input Logic Pin - Serial bus data input/open drain output Logic Pin - Hardwire slave address pin for I2C serial bus. Range: VLOGIC or GND Logic Pin - Hardwire slave address pin for I2C serial bus. Range: VLOGIC or GND DCP "low" terminal DCP wiper terminal DCP "high" terminal Analog power supply. Range 1.7V to 5.5V Ground pin
ISL23315 (10 LD TQFN) TOP VIEW
10 VLOGIC
5
4
A1
6 7
9 8 7 6 GND VCC RH RW
5 6 7 8 9
RL RW RH VCC GND
SCL SDA A0 A1
1 2 3 4 RL 5
8 9 10
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FN7778.0 December 15, 2010
ISL23315 Ordering Information
PART NUMBER (Note 5) ISL23315TFUZ (Notes 1, 3) ISL23315UFUZ (Notes 1, 3) ISL23315WFUZ (Notes 1, 3) PART MARKING 3315T 3315U 3315W RESISTANCE OPTION (k) 100 50 10 100 100 50 50 10 10 TEMP RANGE (C) -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 PACKAGE (Pb-free) 10 Ld MSOP 10 Ld MSOP 10 Ld MSOP 10 Ld 2.1x1.6 TQFN 10 Ld 2.1x1.6 TQFN 10 Ld 2.1x1.6 TQFN 10 Ld 2.1x1.6 TQFN 10 Ld 2.1x1.6 TQFN 10 Ld 2.1x1.6 TQFN PKG. DWG. # M10.118 M10.118 M10.118 L10.2.1x1.6A L10.2.1x1.6A L10.2.1x1.6A L10.2.1x1.6A L10.2.1x1.6A L10.2.1x1.6A
ISL23315TFRUZ-T7A (Notes 2, 4) HB ISL23315TFRUZ-TK (Notes 2, 4) HB
ISL23315UFRUZ-T7A (Notes 2, 4) HA ISL23315UFRUZ-TK (Notes 2, 4) HA
ISL23315WFRUZ-T7A (Notes 2, 4) GZ ISL23315WFRUZ-TK (Notes 2, 4) GZ NOTES:
1. Add "-T*" suffix for Tape and Reel option. Please refer to TB347 for details on reel specifications. 2. Please refer to TB347 for details on reel specifications. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 5. For Moisture Sensitivity Level (MSL), please see device information page for ISL23315. For more information on MSL please see techbrief TB363.
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FN7778.0 December 15, 2010
ISL23315
Absolute Maximum Ratings
Supply Voltage Range VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Voltage on Any DCP Terminal Pin . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Voltage on Any Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Wiper current IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA ESD Rating Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . .6.5kV CDM Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . . . . . . . . 1kV Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 200V Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . 100mA @ +125C
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) 10 Ld MSOP Package (Notes 6, 7) . . . . . . . 170 70 10 Ld TQFN Package (Notes 6, 7) . . . . . . 145 90 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +125C VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7V to 5.5V VLOGIC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2V to 5.5V DCP Terminal Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to VCC Max Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 6. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 7. For JC, the "case temp" location is the center top of the package.
Analog Specifications
SYMBOL RTOTAL PARAMETER RH to RL resistance
VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40C to +125C.
TEST CONDITIONS W option U option T option MIN (Note 20) TYP (Note 8) 10 50 100 -20 W option U option T option 2 175 85 70 0 70 VCC 200 +20 MAX (Note 20) UNITS k k k % ppm/C ppm/C ppm/C V
RH to RL resistance tolerance End-to-End Temperature Coefficient
VRH, VRL RW
DCP terminal voltage Wiper resistance
VRH or VRL to GND RH - floating, VRL = 0V, force IW current to the wiper, IW = (VCC - VRL)/RTOTAL, VCC = 2.7V to 5.5V VCC = 1.7V
580 22/22/32 -0.4 < 0.1 120 190 220 -65 -75 0.4
pF A nV Hz nV Hz nV Hz dB dB
CH/CL/CW
Terminal capacitance Leakage on DCP pins Resistor noise density
See "DCP Macro Model" on page 8 Voltage at pin from GND to VCC Wiper at middle point, W option Wiper at middle point, U option Wiper at middle point, T option
ILkgDCP Noise
Feed Thru PSRR
Digital feed-through from bus to wiper Power Supply Reject Ratio
Wiper at middle point Wiper output change if VCC change 10%; wiper at middle point
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FN7778.0 December 15, 2010
ISL23315
Analog Specifications
SYMBOL PARAMETER
VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40C to +125C. (Continued)
TEST CONDITIONS MIN (Note 20) TYP (Note 8) MAX (Note 20) UNITS
VOLTAGE DIVIDER MODE (0V @ RL; VCC @ RH; measured at RW, unloaded)
INL (Note 13) Integral non-linearity, guaranteed monotonic W option U, T option DNL (Note 12) Differential non-linearity, guaranteed monotonic W option U, T option FSerror (Note 11) Full-scale error W option U, T option ZSerror (Note 10) Zero-scale error W option U, T option TCV Ratiometric temperature coefficient (Notes 14) W option, Wiper Register set to 80 hex U option, Wiper Register set to 80 hex T option, Wiper Register set to 80 hex Large Signal Wiper Settling Time fcutoff -3dB cutoff frequency From code 0 to FF hex Wiper at middle point W option Wiper at middle point U option Wiper at middle point T option -1.0 -0.5 -1 -0.4 -3.5 -2 0 0 0.5 0.15 0.4 0.1 -2 -0.5 2 0.4 8 4 2.3 300 1200 250 120 +1.0 +0.5 +1 +0.4 0 0 3.5 2 LSB (Note 9) LSB (Note 9) LSB (Note 9) LSB (Note 9) LSB (Note 9) LSB (Note 9) LSB (Note 9) LSB (Note 9) ppm/C ppm/C ppm/C ns kHz kHz kHz
RHEOSTAT MODE (Measurements between RW and RL pins with RH not connected, or between RW and RH with RL not connected)
RINL (Note 18) Integral non-linearity, Guaranteed monotonic W option; VCC = 2.7V to 5.5V W option; VCC = 1.7V U, T option; VCC = 2.7V to 5.5V U, T option; VCC = 1.7V RDNL (Note 17) Differential non-linearity, Guaranteed monotonic W option; VCC = 2.7V to 5.5V W option; VCC = 1.7V U, T option; VCC = 2.7V to 5.5V U, T option; VCC = 1.7V -0.5 -1 -1.0 -2.0 1 10.5 0.3 2.1 0.4 0.6 0.15 0.35 +0.5 +1 +1.0 +2.0 MI (Note 15) MI (Note 15) MI (Note 15) MI (Note 15) MI (Note 15) MI (Note 15) MI (Note 15) MI (Note 15)
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FN7778.0 December 15, 2010
ISL23315
Analog Specifications
SYMBOL Roffset (Note 16) PARAMETER Offset, wiper at 0 position
VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40C to +125C. (Continued)
TEST CONDITIONS W option; VCC = 2.7V to 5.5V W option; VCC = 1.7V U, T option; VCC = 2.7V to 5.5V U, T option; VCC = 1.7V 0 MIN (Note 20) 0 TYP (Note 8) 3 6.3 0.5 1.1 220 100 75 2 MAX (Note 20) 5.5 UNITS MI (Note 15) MI (Note 15) MI (Note 15) MI (Note 15) ppm/C ppm/C ppm/C
TCR (Note 19)
Resistance temperature coefficient
W option; Wiper register set between 32 hex and FF hex U option; Wiper register set between 32 hex and FF hex T option; Wiper register set between 32 hex and FF hex
Operating Specifications
SYMBOL ILOGIC PARAMETER
VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40C to +125C.
TEST CONDITIONS VLOGIC = 5.5V, VCC = 5.5V, fSCL = 400 kHz (for I2C active read and write) VLOGIC = 1.2V, VCC = 1.7V, fSCL = 400 kHz (for I2C active read and write) MIN (Note 20) TYP (Note 8) MAX (Note 20) 200 UNITS A
VLOGIC supply current (write/read)
5
A
ICC
VCC supply current (write/read)
VLOGIC = 5.5V, VCC = 5.5V VLOGIC = 1.2V, VCC = 1.7V
18 10 1 0.5 1.5 1 1.3 0.4 0.7 0.5 -0.4 <0.1 1.5 0.4
A A A A A A A A A A A s
ILOGIC SB
VLOGIC standby current
VLOGIC = VCC = 5.5V, I2C interface in standby VLOGIC = 1.2V, VCC = 1.7V, I2C interface in standby
ICC SB
VCC standby current
VLOGIC = VCC = 5.5V, I2C interface in standby VLOGIC = 1.2V, VCC = 1.7V, I2C interface in standby
ILOGIC
SHDN
VLOGIC shutdown current
VLOGIC = VCC = 5.5V, I2C interface in standby VLOGIC = 1.2V, VCC = 1.7V, I2C interface in standby
ICC SHDN
VCC shutdown current
VLOGIC = VCC = 5.5V, I2C interface in standby VLOGIC = 1.2V, VCC = 1.7V, I2C interface in standby
ILkgDig tDCP
Leakage current, at pins A0, A1, SDA, SCL Wiper response time
Voltage at pin from GND to VLOGIC SCL rising edge of the acknowledge bit after data byte to wiper new position
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FN7778.0 December 15, 2010
ISL23315
Operating Specifications
SYMBOL tShdnRec PARAMETER DCP recall time from shutdown mode
VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40C to +125C. (Continued)
TEST CONDITIONS SCL rising edge of the acknowledge bit after ACR data byte to wiper recalled position and RH connection Ramp monotonic at any level 0.01 MIN (Note 20) TYP (Note 8) 1.5 MAX (Note 20) UNITS s
VCC, VLOGIC VCC ,VLOGIC ramp rate Ramp (Note 21)
50
V/ms
Serial Interface Specification
SYMBOL VIL VIH Hysteresis PARAMETER Input LOW Voltage Input HIGH Voltage SDA and SCL Input Buffer Hysteresis SDA Output Buffer LOW Voltage
for SCL, SDA, A0, A1 Unless Otherwise Noted.
TEST CONDITIONS MIN (Note 20) -0.3 0.7 x VLOGIC VLOGIC > 2V VLOGIC <2V IOL = 3mA, VLOGIC > 2V IOL = 1.5mA, VLOGIC <2V 0.05 x VLOGIC 0.1 x VLOGIC 0 0.4 0.2 x VLOGIC 10 400 Any pulse narrower than the max spec is suppressed SCL falling edge crossing 30% of VLOGIC, until SDA exits the 30% to 70% of VLOGIC window SDA crossing 70% of VLOGIC during a STOP condition, to SDA crossing 70% of VLOGIC during the following START condition Measured at the 30% of VLOGIC crossing Measured at the 70% of VLOGIC crossing SCL rising edge to SDA falling edge; both crossing 70% of VLOGIC From SDA falling edge crossing 30% of VLOGIC to SCL falling edge crossing 70% of VLOGIC From SDA exiting the 30% to 70% of VLOGIC window, to SCL rising edge crossing 30% of VLOGIC From SCL falling edge crossing 70% of VCC to SDA entering the 30% to 70% of VCC window 1300 50 900 V V pF kHz ns ns TYP (Note 8) MAX (Note 20) 0.3 x VLOGIC VLOGIC + 0.3 UNITS V V V
VOL
Cpin fSCL tsp tAA
SDA, SCL Pin Capacitance SCL Frequency Pulse Width Suppression Time at SDA and SCL Inputs SCL Falling Edge to SDA Output Data Valid Time the Bus Must be Free Before the Start of a New Transmission
tBUF
ns
tLOW tHIGH tSU:STA
Clock LOW Time Clock HIGH Time START Condition Set-up Time
1300 600 600
ns ns ns
tHD:STA
START Condition Hold Time
600
ns
tSU:DAT
Input Data Set-up Time
100
ns
tHD:DAT
Input Data Hold Time
0
ns
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FN7778.0 December 15, 2010
ISL23315
Serial Interface Specification
SYMBOL tSU:STO PARAMETER STOP Condition Set-up Time
for SCL, SDA, A0, A1 Unless Otherwise Noted. (Continued)
TEST CONDITIONS From SCL rising edge crossing 70% of VLOGIC, to SDA rising edge crossing 30% of VLOGIC MIN (Note 20) 600 TYP (Note 8) MAX (Note 20) UNITS ns
tHD:STO
STOP Condition Hold Time for Read From SDA rising edge to SCL or Write falling edge; both crossing 70% of VCC (Note 11) Output Data Hold Time From SCL falling edge crossing 30% of VLOGIC, until SDA enters the 30% to 70% of VLOGIC window. IOL = 3mA, VLOGIC > 2V. IOL = 0.5mA, VLOGIC < 2V From 30% to 70% of VLOGIC From 70% to 30% of VLOGIC Total on-chip and off-chip (Note 11) Before START condition After STOP condition
1300
ns
tDH
0
ns
tR tF Cb tSU:A tHD:A NOTES:
SDA and SCL Rise Time SDA and SCL Fall Time Capacitive Loading of SDA or SCL A1, A0 setup time A1, A0 hold time
20 + 0.1 x Cb 20 + 0.1 x Cb 10 600 600
250 250 400
ns ns pF ns ns
8. Typical values are for TA = +25C and 3.3V supply voltages. 9. LSB = [V(RW)255 - V(RW)0]/255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 10. ZS error = V(RW)0/LSB. 11. FS error = [V(RW)255 - VCC]/LSB. 12. DNL = [V(RW)i - V(RW)i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting. 13. INL = [V(RW)i - i * LSB - V(RW)0]/LSB for i = 1 to 255 Max ( V ( RW ) i ) - Min ( V ( RW ) i ) for i = 16 to 255 decimal, T = -40C to +125C. Max( ) is the maximum value of the wiper 10 6 TC V = ----------------------------------------------------------------------------- x --------------------voltage and Min( ) is the minimum value of the wiper voltage over the temperature range. V ( RW i ( +25C ) ) +165C 15. MI = |RW255 - RW0|/255. MI is a minimum increment. RW255 and RW0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively. 14. 16. Roffset = RW0/MI, when measuring between RW and RL. Roffset = RW255/MI, when measuring between RW and RH. 17. RDNL = (RWi - RWi-1)/MI -1, for i = 16 to 255. 18. RINL = [RWi - (MI * i) - RW0]/MI, for i = 16 to 255. 19.
6 for i = 16 to 255, T = -40C to +125C. Max( ) is the maximum value of the resistance and Min( ) is the [ Max ( Ri ) - Min ( Ri ) ] 10 TC R = ------------------------------------------------------ x --------------------- minimum value of the resistance over the temperature range. Ri ( +25C ) +165C 20. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
21. It is preferable to ramp up both the VLOGIC and the VCC supplies at the same time. If this is not possible it is recommended to ramp-up the VLOGIC first followed by the VCC.
DCP Macro Model
RTOTAL RH CH CW CL 22pF RL
22pF RW
32pF
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FN7778.0 December 15, 2010
ISL23315 Timing Diagrams
SDA vs SCL Timing
tF tHIGH tLOW tR tsp
SCL tSU:STA SDA (INPUT TIMING)
tSU:DAT tHD:DAT tSU:STO
tHD:STA
tAA SDA (OUTPUT TIMING)
tDH
tBUF
A0 and A1 Pin Timing
START SCL CLK 1 STOP
SDA tSU:A A0, A1 tHD:A
Typical Performance Curves
0.4 0.30
0.2
DNL (LSB) DNL (LSB)
0.15
0
0
-0.2
-0.15
-0.4 0 50 100 150 200 250 TAP POSITION (DECIMAL)
-0.30
0
50
100
150
200
250
TAP POSITION (DECIMAL)
FIGURE 3. 10k DNL vs TAP POSITION, VCC = 5V
FIGURE 4. 50k DNL vs TAP POSITION, VCC = 5V
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FN7778.0 December 15, 2010
ISL23315 Typical Performance Curves
0.4
(Continued)
0.30
0.2
INL (LSB) INL (LSB)
0.15
0
0
-0.2
-0.15
-0.4 0 50 100 150 200 250 TAP POSITION (DECIMAL)
-0.30 0 50 100 150 200 250 TAP POSITION (DECIMAL)
FIGURE 5. 10k INL vs TAP POSITION, VCC = 5V
FIGURE 6. 50k INL vs TAP POSITION, VCC = 5V
0.4
0.30
0.2
RDNL (MI)
0.15
RDNL (MI)
0
0
-0.2
-0.15
-0.4
0
50
100
150
200
250
-0.30
0
50
TAP POSITION (DECIMAL)
100 150 TAP POSITION (DECIMAL)
200
250
FIGURE 7. 10k RDNL vs TAP POSITION, VCC = 5V
FIGURE 8. 50k RDNL vs TAP POSITION, VCC = 5V
0.6 0.4
0.30
0.15 0.2
RINL (MI) RINL (MI)
0 -0.2
0
-0.15 -0.4 -0.6 -0.30 0 50 100 150 200 250 TAP POSITION (DECIMAL)
0
50
100
150
200
250
TAP POSITION (DECIMAL)
FIGURE 9. 10k RINL vs TAP POSITION, VCC = 5V
FIGURE 10. 50k RINL vs TAP POSITION, VCC = 5V
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FN7778.0 December 15, 2010
ISL23315 Typical Performance Curves
70 +125C 60
WIPER RESISTANCE ()
(Continued)
60 +125C 50 +25C
50 40 30 20 10 0 0 50
+25C
WIPER RESISTANCE ()
40 30 20 10 0
-40C
-40C
100 150 TAP POSITION (DECIMAL)
200
250
0
50
100
150
200
250
TAP POSITION (DECIMAL)
FIGURE 11. 10k WIPER RESISTANCE vs TAP POSITION, VCC = 5V
FIGURE 12. 50k WIPER RESISTANCE vs TAP POSITION, VCC = 5V
300 250 200 150 100 50 0 15
70 60 50
TCv (ppm/C)
TCv (ppm/C)
40 30 20 10 0 15
65
115
165
215
65
115
165
215
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 13. 10k TCv vs TAP POSITION
FIGURE 14. 50k TCv vs TAP POSITION
600 500
200
150
TCr (ppm/C) TCr (ppm/C)
400 300 200 100 0 15
100
50
65
115
165
215
0 15
65
115
165
215
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 15. 10k TCr vs TAP POSITION
FIGURE 16. 50k TCr vs TAP POSITION
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FN7778.0 December 15, 2010
ISL23315 Typical Performance Curves
35 30 25
TCv (ppm/C)
(Continued)
120
90
TCr (ppm/C)
20 15 10 5 0 15
60
30
65
115
165
215
0 15
65
TAP POSITION (DECIMAL)
115 165 TAP POSITION (DECIMAL)
215
FIGURE 17. 100k TCv vs TAP POSITION
FIGURE 18. 100k TCr vs TAP POSITION
SCL CLOCK
RW PIN
10mV/DIV 1s/DIV
20mV/DIV 5s/DIV
FIGURE 19. WIPER DIGITAL FEED-THROUGH
FIGURE 20. WIPER TRANSITION GLITCH
1V/DIV 1s/DIV WIPER
1V/DIV 0.1s/DIV
SCL 9TH CLOCK OF THE DATA BYTE (ACK)
FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME
FIGURE 22. POWER-ON START-UP IN VOLTAGE DIVIDER MODE
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FN7778.0 December 15, 2010
ISL23315 Typical Performance Curves
CH1: 0.5V/DIV, 0.2s/DIV RH PIN CH2: 0.2V/DIV, 0.2s/DIV RW PIN
STANDBY CURRENT ICC (A)
(Continued)
1.2 1.0 0.8 0.6 0.4 0.2 0 -40 VCC = 1.7V, VLOGIC = 1.2V
VCC = 5.5V, VLOGIC = 5.5V
RTOTAL = 10k -3dB FREQUENCY = 1.4MHz AT MIDDLE TAP
-15
10
35
60
85
110
TEMPERATURE (C)
FIGURE 23. 10k -3dB CUT OFF FREQUENCY
FIGURE 24. STANDBY CURRENT vs TEMPERATURE
Functional Pin Descriptions
Potentiometers Pins
RH AND RL
The high (RH) and low (RL) terminals of the ISL23315 are equivalent to the fixed terminals of a mechanical potentiometer. RH and RL are referenced to the relative position of the wiper and not the voltage potential on the terminals. With WR set to 255 decimal, the wiper will be closest to RH, and with the WR set to 0, the wiper is closest to RL.
VLOGIC This is an input pin, that supply internal level translator for serial bus operation from 1.2V to 5.5V.
Principles of Operation
The ISL23315 is an integrated circuit incorporating one DCP with its associated registers and an I2C serial interface providing direct communication between a host and the potentiometer. The resistor array is comprised of individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The electronic switches on the device operate in a "make before break" mode when the wiper changes tap positions. Voltage at any DCP pins, RH, RL or RW, should not exceed VCC level at any conditions during power-up and normal operation. The VLOGIC pin needs to be connected to the I2C bus supply which allows reliable communication with the wide range of microcontrollers and independent of the VCC level. This is extremely important in systems where the master supply has lower levels than DCP analog supply.
RW
RW is the wiper terminal, and it is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WR register.
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bidirectional serial data input/output pin for I2C interface. It receives device address, operation code, wiper address and data from an I2C external master device at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock. SDA requires an external pull-up resistor, since it is an open drain input/output.
DCP Description
The DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin of the DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by an 8-bit volatile Wiper Register (WR). When the WR of a DCP contains all zeroes (WR[7:0]= 00h), its wiper terminal (RW) is closest to its "Low" terminal (RL). When the WR register of a DCP contains all ones (WR[7:0]= FFh), its wiper terminal (RW) is closest to its "High" terminal (RH). As the value of the WR increases from all zeroes (0) to all ones (255 decimal), the wiper moves monotonically from the position closest to RL to the position closest to RH. At the same time, the
FN7778.0 December 15, 2010
SERIAL CLOCK (SCL)
This input is the serial clock of the I2C serial interface. SCL requires an external pull-up resistor, since a master is an open drain output.
DEVICE ADDRESS (A1, A0)
The address inputs are used to set the least significant 2 bits of the 7-bit I2C interface slave address. A match in the slave address serial data stream must match with the Address input pins in order to initiate communication with the ISL23315. A maximum of four ISL23315 devices may occupy the I2C serial bus (see Table 3). 13
ISL23315
resistance between RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. While the ISL23315 is being powered up, the WR is reset to 80h (128 decimal), which locates RW roughly at the center between RL and RH. The WR can be read or written to directly using the I2C serial interface as described in the following sections. indicating START and STOP conditions (see Figure 26). On power-up of the ISL23315, the SDA pin is in the input mode. All I2C interface operations must begin with a START condition, which is a HIGH-to-LOW transition of SDA while SCL is HIGH. The ISL23315 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (see Figure 26). A START condition is ignored during the power-up of the device. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 26). A STOP condition at the end of a read operation or at the end of a write operation places the device in its standby mode. An ACK (Acknowledge) is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (see Figure 27). The ISL23315 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL23315 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation. A valid Identification Byte contains 10100 as the five MSBs, and the following two bits matching the logic values present at pins A1 and A0. The LSB is the Read/Write bit. Its value is "1" for a Read operation and "0" for a Write operation (see Table 3).
TABLE 3. IDENTIFICATION BYTE FORMAT
LOGIC VALUES AT PINS A1 AND A0, RESPECTIVELY
Memory Description
The ISL23315 contains two volatile 8-bit registers: Wiper Register (WR) and Access Control Register (ACR). Memory map of ISL23315 is in Table 1. The Wiper Register (WR) at address 0, contains current wiper position. The Access Control Register (ACR) at address 10h contains information and control bits described in Table 2.
TABLE 1. MEMORY MAP ADDRESS (hex) 10 0 VOLATILE REGISTER NAME ACR WR DEFAULT SETTING (hex) 42 80
TABLE 2. ACCESS CONTROL REGISTER (ACR) BIT # NAME/ VALUE 7 0 6 SHDN 5 0 4 0 3 0 2 0 1 1 0 0
The SHDN bit (ACR[6]) disables or enables Shutdown mode. When this bit is 0, i.e. DCP is forced to end-to-end open circuit and RW is shorted to RL as shown in Figure 25. Default value of the SHDN bit is 1.
RH
RW
1 (MSB)
0
1
0
0
A1
A0
R/W (LSB)
RL
FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE
I2C Serial Interface
The ISL23315 supports an I2C bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL23315 operates as a slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for
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ISL23315
SCL
SDA
START
DATA STABLE
DATA CHANGE
DATA STABLE
STOP
FIGURE 26. VALID DATA CHANGES, START AND STOP CONDITIONS
SCL FROM MASTER
1
8
9
SDA OUTPUT FROM TRANSMITTER
HIGH IMPEDANCE
SDA OUTPUT FROM RECEIVER START
HIGH IMPEDANCE
ACK
FIGURE 27. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE SIGNALS FROM THE MASTER S T A R T S T O P
IDENTIFICATION BYTE
ADDRESS BYTE
DATA BYTE
SIGNAL AT SDA SIGNALS FROM THE SLAVE
1 0 1 0 0 A1 A0 0 A C K
000 A C K A C K
FIGURE 28. BYTE WRITE SEQUENCE
SIGNALS FROM THE MASTER
S T A R T
IDENTIFICATION BYTE WITH R/W = 0
ADDRESS BYTE
S T A R T
READ IDENTIFICATION BYTE WITH R/W = 1 A C K A C K S AT CO KP
SIGNAL AT SDA
1 0 1 0 0 A1 A0 0 A C K
000 A C K
1 0 1 0 0 A1 A0 1 A C K
SIGNALS FROM THE SLAVE
FIRST READ DATA BYTE
LAST READ DATA BYTE
FIGURE 29. READ SEQUENCE
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ISL23315
Write Operation
A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL23315 responds with an ACK. The data is transferred from I2C block to the corresponding register at the 9th clock of the data byte and device enters its standby state (see Figures 27 and 28).
Applications Information
VLOGIC Requirements
It is recommended to keep VLOGIC powered all the time during normal operation. In a case where turning VLOGIC OFF is necessary, it is recommended to ground the VLOGIC pin of the ISL23315. Grounding the VLOGIC pin or both VLOGIC and VCC does not affect other devices on the same bus. It is good practice to put a 1F cap in parallel to 0.1F as close to the VLOGIC pin as possible.
Read Operation
A Read operation consists of a three byte instruction followed by one or more Data Bytes (see Figure 29). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to "0", an Address Byte, a second START, and a second Identification byte with the R/W bit set to "1". After each of the three bytes, the ISL23315 responds with an ACK; then the ISL23315 transmits Data Byte. The master terminates the read operation issuing a NACK (ACK) and a STOP condition following the last bit of the last Data Byte (see Figure 29).
VCC Requirements and Placement
It is recommended to put a 1F capacitor in parallel with 0.1F decoupling capacitor close to the VCC pin.
Wiper Transition
When stepping up through each tap in voltage divider mode, some tap transition points can result in noticeable voltage transients, or overshoot/undershoot, resulting from the sudden transition from a very low impedance "make" to a much higher impedance "break" within a short period of time (<1s). There are several code transitions such as 0Fh to 10h, 1Fh to 20h,..., EFh to FFh, which have higher transient glitch. Note, that all switching transients will settle well within the settling time as stated in the datasheet. A small capacitor can be added externally to reduce the amplitude of these voltage transients. However, that will also reduce the useful bandwidth of the circuit, thus may not be a good solution for some applications. It may be a good idea, in that case, to use fast amplifiers in a signal chain for fast recovery.
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FN7778.0 December 15, 2010
ISL23315 Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev.
DATE 12/15/10 REVISION FN7778.0 Initial Release CHANGE
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL23315 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com
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FN7778.0 December 15, 2010
ISL23315
Mini Small Outline Plastic Packages (MSOP)
N
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1 -BE
INCHES SYMBOL MIN 0.037 0.002 0.030 0.007 0.004 0.116 0.116 0.187 0.016 10 0.003 0.003 5o 0o 15o 6o MAX 0.043 0.006 0.037 0.011 0.008 0.120 0.120 0.199 0.028 A
ABC
MILLIMETERS MIN 0.94 0.05 0.75 0.18 0.09 2.95 2.95 4.75 0.40 10 0.07 0.07 5o 0o 15o 6o MAX 1.10 0.15 0.95 0.27 0.20 3.05 3.05 5.05 0.70 NOTES 9 3 4 6 7 Rev. 0 12/02
INDEX AREA
12 TOP VIEW
0.20 (0.008)
A1 A2
4X
0.25 (0.010) GAUGE PLANE SEATING PLANE -C-
R1 R
b c D E1
A
A2
4X
L L1
e E L L1 N R
0.020 BSC
0.50 BSC
A1
-He D
b
0.10 (0.004) -A0.20 (0.008)
C
SEATING PLANE
0.037 REF
0.95 REF
C a C L E1
C
R1
SIDE VIEW
-B-
0.20 (0.008)
CD
END VIEW
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension "D" does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (.004) at seating Plane. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
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FN7778.0 December 15, 2010
ISL23315
Package Outline Drawing
L10.2.1x1.6A
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 5, 3/10
8. PIN 1 INDEX AREA 2.10 B 1 A PIN #1 ID 8. 0.10 MIN. 1.60 10 1 0.05 MIN.
4 4X 0.20 MIN.
5
0.80 0.10 2X TOP VIEW BOTTOM VIEW 9 6X 0.50 6 10 X 0.20 4 0.10 M C A B MC SEE DETAIL "X" PACKAGE OUTLINE MAX. 0.55 0.10 C C (0.10 MIN.) (2.00) SIDE VIEW (1.30) SEATING PLANE 0.08 C 10X 0.40
(10 X 0.20)
(0.05 MIN) 1
(10X 0.60)
(0.80)
C (6X 0.50 ) (2.50)
0 . 125 REF
0-0.05 TYPICAL RECOMMENDED LAND PATTERN DETAIL "X"
NOTES: 1. 2. 3. 4. Dimensioning and tolerancing conform to ASME Y14.5M-1994. All Dimensions are in millimeters. Angles are in degrees. Dimensions in ( ) for Reference Only. Unless otherwise specified, tolerance : Decimal 0.05 Lead width dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. Maximum package warpage is 0.05mm. Maximum allowable burrs is 0.076mm in all directions. Same as JEDEC MO-255UABD except: No lead-pull-back, MIN. Package thickness = 0.45 not 0.50mm Lead Length dim. = 0.45mm max. not 0.42mm. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
5. 6. 7.
8.
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FN7778.0 December 15, 2010

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